verilog - Scope of `define macros -

this question regarding system verilog macros.
have top-module, sub-module , sub-sub module. sub-sub module instantiated in sub-module instantiated in top module.

if define macro `define abc in sub module, code written inside `ifndef abc gets compiled in top module/sub-sub module

the scope of `define macros , other compiler directives compilation unit. compilation unit stream of source text compiler parses. macro gets defined @ point appears in compilation unit , visible point onward.

the scopes defined modules , other namespaces irrelevant because macros pre-processed before verilog or systemverilog syntax gets recognized. means can never have instance specific control on macro definitions.

there sight difference between how verilog , systemverilog define compilation unit.

in verilog, each compilation unit compilation step, or 1 invocation of tool compiles source code. tools have 1 compilation step, requiring compile source code in 1 step. other tools (e.g. modelsim), allow compile code in separate steps. `define macro in 1 compilation step not visible other compilation steps unless re-define it.

systemverilog adds ability treat each file on compilers command line separate compilation unit. needed because systemverilog allows define things typedefs , functions outside of module. keeping each file separate compilation unit prevents naming collisions. (this compilation unit behavior same in c/c++).

because of way people mix legacy verilog code systemverilog, tools allow choose verilog or systemverilog behavior of compilation unit.